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july 2013 docid023918 rev 1 1/20 AN4200 application note four-layer demonstration bo ard based on the sta333is introduction the steval-cca053v1 is a four-layer demons tration board designed for the evaluation of the sta333is two-channel, high-efficiency sound terminal ? device. the purpose of this application note is to show: ? how to connect the sta333is demonstration board ? the performance of the sta333is device ? how to avoid critical board and layout issues all the results and characterization data included in this application note have been measured using audio precision equipment. re ference documents consist of the sta333is datasheet, schematic diagrams and pcb layout. figure 1. steval-cca053v1 www.st.com
contents AN4200 2/20 docid023918 rev 1 contents 1 test conditions and connections of dem onstration board . . . . . . . . . . 4 1.1 power supply signal and interface connection . . . . . . . . . . . . . . . . . . . . . . 4 1.2 output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 required equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 board connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 schematic diagram and pcb lay out . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 apworkbench settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 thermal test - v cc = 12.5 v, 1 khz, load= 8 w (ste reo) . . . . . . . . . . . . . 14 5.1 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 design guidelines for schematic and pcb layout . . . . . . . . . . . . . . . . 15 6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 snubber network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.4 pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4.1 snubber layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4.2 v cc traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4.3 ground plane and heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4.4 output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4.5 v cc filter for high frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
docid023918 rev 1 3/20 AN4200 list of figures 20 list of figures figure 1. steval-cca053v1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. demonstration board (four-layer) - connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. schematic diagram - part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. schematic diagram - part 2 (connectors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. sta333is demonstration board - four-layer pcb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. apworkbench - device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. apworkbench - control panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. thd+n vs. power - v cc = 12.5 v, load = 8 w, 1 khz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. thd+n vs. frequency - v cc = 12.5 v, load = 8 w, pout = 1 w at 1 khz . . . . . . . . . . . . . . 10 figure 10. frequency response - v cc = 12.5 v, load = 8 w, pout = 1 w at 1 khz . . . . . . . . . . . . . . . 11 figure 11. crosstalk - v cc = 12.5 v, load = 8 w, pout = 1 w at 1 khz . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 12. fft - v cc = 12.5 v, load = 8 w, pout = 1 w at 1 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 13. output power vs. supply voltage - load = 8 w, 1 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 14. efficiency - v cc = 12.5 v, 1 khz, load = 8 w (stereo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 15. thermal analysis - v cc = 12.5 v - 2 x 10 w at 1 khz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 16. snubber network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 17. pcb layout recommendations - star routing v cc traces. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 18. pcb layout recommendation - large ground plan e on the top side . . . . . . . . . . . . . . . . . . 17 figure 19. pcb layout recommendation - large ground plan e on the inner layer 2 . . . . . . . . . . . . . . . 17 figure 20. pcb layout recommendation - large ground plan e on the inner layer 3 . . . . . . . . . . . . . . . 17 figure 21. pcb layout recommendation - large ground pl ane on the bottom side . . . . . . . . . . . . . . . 17 figure 22. output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 23. v cc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
test conditions and connections of demonstration board AN4200 4/20 docid023918 rev 1 1 test conditions and connections of demonstration board 1.1 power supply signal and interface connection 1. connect the power supply to the +v cc and gnd terminal blocks (j2) 2. connect the steval-cca053v1 interface board to the j4 connector 3. connect the s/pdif signal cable to the rca jack on the steval-cca035v1 board. the signal source should be the audi o precision equipment or a dvd player. 4. adjust the voltage level of the power supply. the voltage range of the dc power supply is 4.5 v to 18 v. 5. connect the load to the connectors j1 and j3 1.2 output configuration the sta333is demonstration board can be only configured for 2.0 channels and btl outputs. 1.3 required equipment ? audio precision (system 2700) ? audio analyzer: mod. sys2722 -192k ? class-d filter: aux-0025 filter ? multifunction module: dcx-127 ? dc power supply (4.5 v to 18 v) ? lambda genesys gen 80-19 ? hp 6038a ? digital oscilloscope: tektronix tds5054b ? digital multimeter: agilent mod. 34410a ? pc with apworkbench control software installed
docid023918 rev 1 5/20 AN4200 test conditions and connections of demonstration board 20 1.4 board connections figure 2. demonstration board (four-layer) - connectors j4 connect to steval-cca035v board j1 out1 j3 out2 j2 dc supply
schematic diagram and pcb layout AN4200 6/20 docid023918 rev 1 2 schematic diagram and pcb layout 2.1 schematic figure 3. schemati c diagram - part 1
docid023918 rev 1 7/20 AN4200 schematic diagram and pcb layout 20 figure 4. schematic diagram - part 2 (connectors) 2.2 pcb layout figure 5. steval-cca053v1 board - four-layer pcb note: please refer to figure 18 through figure 21 on page 17 for the top, inner layer 2, inner layer 3, and bottom views, respectively.
schematic diagram and pcb layout AN4200 8/20 docid023918 rev 1 2.3 bill of material table 1. bill of material no. type footprint description qty reference manufacturer 1 connector through-hole 2p pitch: 5 mm connector terminal 3 j1, j2, j3 any source 2 header through-hole 16p (8 x 2 row) 2.5 mm header 1 j4 any source 3 ccap cap0603 50 volt npo 330 pf ? 10% 2 c12, c13 murata 4 ccap cap0603 50 volt 1nf ? 10% 6 c1, c2, c3, c4, c5, c6 murata 5 ccap cap0603 50 volt 100 nf ? 10% 6 c20, c21, c22, c23, c24, c27 murata 6 ccap cap1206 50 volt 1u ? 10% 2 c16, c17 murata 7 ecap cap1206 10 f / 16 v 5 c7, c8, c10, c11, c30 samsung 8res r12066r2, ? 5% 1/8w 4 r1, r2, r5, r6 murata 9 res r1206 20 ? 5% 1/8w 2 r3, r4 murata 10 res r0603 2r2 ? 5% 1/16w 1 r7 murata 11 res r0603 ns 2 r8, r12 12 plastic rod hexagonal rod 15 mm length, male type 4 four corners any source 13 plastic rod hexagonal rod 8 mm length, female type 4 four corners any source 14 ic csp 5x6 array sta333is 1 ic1 stmicroelectronics 15 coil smd dpm02, maruwa 2 l5, l6 maruwa 16 pcb sta333is 4-layer 1v0 1 fastprint
docid023918 rev 1 9/20 AN4200 apworkbench settings 20 3 apworkbench settings figure 6. apworkbench - device selection figure 7. apworkbench - control panel device selection interface selection sound terminal amplifiers volume control gain control bridge enable button
test results AN4200 10/20 docid023918 rev 1 4 test results figure 8. thd+n vs. power - v cc = 12.5 v, load = 8 ? , 1 khz figure 9. thd+n vs. frequency - v cc = 12.5 v, load = 8 ? , pout = 1 w at 1 khz color sweep trac e line style thic k data axis comment 1 1 red solid 2 anlr.thd+n ratio left ch1; vcc= 12.5v, 1khz, 8ohm 1 3 blue solid 2 anlr.thd+n ratio left ch2; vcc= 12.5v, 1khz, 8ohm 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 20 2m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10 w color sweep trac e line style thic k data axis comment 1 1 red solid 2 anlr.thd+n ratio left ch1; vcc= 12.5v, 1w@1khz, 8ohm 1 2 blue solid 2 anlr.thd+n ratio left ch2; vcc= 12.5v, 1w@1khz, 8ohm 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz
docid023918 rev 1 11/20 AN4200 test results 20 figure 10. frequency response - v cc = 12.5 v, load = 8 ? , pout = 1 w at 1 khz figure 11. crosstalk - v cc = 12.5 v, load = 8 ? , pout = 1 w at 1 khz color sweep trac e line style thic k data axis comment 1 1 red solid 2 anlr.level a left ch1; vcc= 12.5v, 1khz, 8ohm 1 2 blue solid 2 anlr.level b right ch1; vcc= 12.5v, 1khz, 8ohm -3 +3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 d b r b -3 +3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz color sweep trac e line style thic k data axis comment 1 1 red solid 2 anlr.crosstalk left ch2 =off; vcc=12.5v, ref:0db@1w@1khz, 8ohm 1 2 blue solid 2 anlr.crosstalk left ch1 =off; vcc=12.5v, ref:0db@1w@1khz, 8ohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -160 -140 -120 -100 -80 -60 -40 -20 d b tttt tt t ttt tt
test results AN4200 12/20 docid023918 rev 1 figure 12. fft - v cc = 12.5 v, load = 8 ? , pout = 1 w at 1 khz figure 13. output power vs. supply voltage - load = 8 ? , 1 khz color sweep trac e line style thic k data axis comment 1 1 red solid 2 fft.ch.1 ampl left ch1; vcc=12.5v; 1w@1khz; 1 2 blue solid 2 fft.ch.2 ampl left ch2; vcc=12.5v; 1w@1khz; -180 +0 -160 -140 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz color sweep trac e line style thic k data axis comment 1 1 red solid 2 anlr.level a left ch1; undistorted output; (1khz - gain=0db) 1 3 blue solid 2 anlr.level b left ch2; thd?10%; (1khz - gain=+3db) +4 +20 +6 +8 +10 +12 +14 +16 +18 vdc 0 30 2 4 6 8 10 12 14 16 18 20 22 24 26 28 w
docid023918 rev 1 13/20 AN4200 test results 20 figure 14. efficiency - v cc = 12.5 v, 1 khz, load = 8 ? (stereo)
thermal test - v cc = 12.5 v, 1 khz, load= 8 w (stereo) AN4200 14/20 docid023918 rev 1 5 thermal test - v cc = 12.5 v, 1 khz, load= 8 ? (stereo) 5.1 test conditions v cc =12.5 vdc load= 8 ? (resistive dummy load) gain= +3 db (both l&r channels) all channels on ap filter= 22 hz 22 khz output power: 2 x 10 w (adj. using post-scale) t amb = 31 c 5.2 test results t max = 88.6 c t amb = 31 c ? t = 57.6 c figure 15. thermal analysis - v cc = 12.5 v - 2 x 10 w at 1 khz
docid023918 rev 1 15/20 AN4200 design guidelines for schematic and pcb layout 20 6 design guidelines for schematic and pcb layout 6.1 general ? absolute maximum rating: 20 v ? bypass capacitor 100 nf in parallel to 1 f and 10 f for each power v cc branch. preferable dielectric is x7r. ? vdd and ground for the digital section should be separated from the other power supply. ? coil saturation current compatible with the peak current of the application 6.2 decoupling capacitors the decoupling capacitors can be shared for each v cc branch. the decoupling capacitors must be placed as close as possible to the ic pins. the capacitor and the decoupling capacitor must be on the same layer as well as the track used to connect the capacitors and the positive v cc device pins. 6.3 snubber network the snubber circuit must be optimized for the specific application. starting values are 330 pf in series to 22 ? . the power dissipation in this network can be defined by the following formula which considers the power supply, frequency and capacitor value: p = c freq pwm (2 v out ) 2 this power is dissipated on the series resistance.
design guidelines for schematic and pcb layout AN4200 16/20 docid023918 rev 1 6.4 pcb layout 6.4.1 snubber layout solder the snubber network as close as possible to the related ic pin. figure 16. snubber network 6.4.2 v cc traces design the pcb tracks to implem ent a star routing for the v cc traces. figure 17. pcb layout recommendations - star routing v cc traces snubber network star routing for vcc traces
docid023918 rev 1 17/20 AN4200 design guidelines for schematic and pcb layout 20 6.4.3 ground plane and heatsink to dissipate the power not delivered to the loads, a large ground plane should be implemented. this solution allows removing the heat from the device without adding an external heatsink. note: it is mandatory to have a large ground plane on the top layer, inner layer 2, inner layer 3, and the bottom layer and solder the slug on the pcb. figure 18. pcb layout recommendation - large ground plane on the top side figure 19. pcb layout recommendation - large ground plane on the inner layer 2 figure 20. pcb layout recommendation - large ground plane on the inner layer 3 figure 21. pcb layout recommendation - large ground plane on the bottom side
design guidelines for schematic and pcb layout AN4200 18/20 docid023918 rev 1 6.4.4 output filter it is recommended to design the pcb using symmetrical paths and tracks. figure 22. output filter 6.4.5 v cc filter for high frequency the v cc filter capacitors must be placed as cl ose as possible to the supply pins. the ceramic capacitors must be positioned on the same layer of the device (in this demonstration board, on the top layer of the pcb) and the distance from the ic must be short and compatible with the minimum smb mounting limitation. figure 23. v cc filter the pwm frequency is 384 khz (with fs = 48 khz) with very fast transition time. in order to compensate the inductive effect of the copper track, the ceramic capacitors must be placed as close as possible to the supply pins. the recommended distance between the capacitors and the supply pins is less than 5 mm. output of symmetrical paths
docid023918 rev 1 19/20 AN4200 revision history 20 7 revision history table 2. document revision history date revision changes 01-jul-2013 1 initial release.
AN4200 20/20 docid023918 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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